1. Field of the Invention
The present invention is in the field of error detection for memories of data processing systems, and, in particular, it relates to error detection for partial write operations of such memories.
2. General Description of the Prior Art
It has been a consistent goal in data processing to achieve faster and faster computing rates. Coupled with this goal of faster computing rates is a parallel goal of providing system architecture that provides for general purpose computing operations. In the past, it has been common for data processing systems to have system architectures that are designed for a fixed data word length. Often, the data word length is selected to be compatible with the data word storage register capacity of the main memory system. For example, if 36-memory registers are employed, it was common to have the data processing system also function on a 36-bit basis.
At a relatively early time in the development of binary computing systems, it was recognized that a more efficient utilization of the main memory could be accomplished by providing for half-word access to the main memory system for reading and writing operations. Such systems usually were operated on a whole-word basis in arithmetic operations, even though access could be made to the memory on a half-word basis.
As system architecture and memory systems were further improved and refined, systems were developed that permitted access for reading and writing in the main memory selectively on the basis of quarter-words, third-words, as well as half-words on a fixed bit-arrangement basis. These binary data processing systems were normally arranged with the memory register capacity being fixed at some multiple of two power, these fractional arrangements were relatively easy to define and implement. In U.S. Pat. No. 4,520,439 issued May 28, 1985, in the name of Arnolds E. Liepa, which is assigned to the assignee of the present invention, provision was made for providing the capability of writing variable length bit-fields, where the bit-field length could vary anywhere from a single bit to the full memory word.
Many logical and data manipulative operations now require the ability to read and write various variable length bit-fields. Such operations are often accomplished by logical instructions coupled with shifting of data words to accomplish the insertion of variable bit-fields in data words to be recorded. Checking of the operation of the partial write function in such systems is vital. Although parity and check bits are generated for merged data and stoed in memory in prior partial write operations, it is possible in such systems to drop or pick up a "1" bit during merging and not detect the error. The present invention provides for the detection of merging errors in order to minimize the occurrence of undetected errors.